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SH4 SDRAM I/F†
SDRAMの設定値の確認†
結構適当になってるからねー。
- CPU:HD6417751RF240(SH7751R 240MHz QFP)
- Area=3
- 32bit access
- size=64MByte
- CPU_Clk=240MHz Bus_clk=60MHz P_clk=30MHz
- 現在の設定値(WPAR01)
| name | address | value | description |
|---|
| BCR1 | 0xFF800000 | 0x00200008 | Area 1 ByteControl Mode, Area 3 SDRAM |
| BCR2 | 0xFF800004 | 0x2DFC | Area 1:32bit Area 2:32bit Area 3:32bit Area 4:8bit Area 5:32bit Area 6:16bit |
| BCR3 | 0xFF800050 | 0x0001 | SDRAM Burst length setting 4 |
| BCR4 | 0xFE0A00F0 | 0x00000000 | Ansync settings |
| WCR1 | 0xFF800008 | 0x02770731 | Device-inter-cycle: 2-wait A6:2 A5:15 A4:15 A3:0 A2:15 A1:1 A0:1 |
| WCR2 | 0xFF80000C | 0x7FFE4EE7 | A6:15 A6B:7 A5:15 A5B:7 A4:15 A3:2 A2:1 A1:15 A0:9 A0B:7 |
| WCR3 | 0xFF800010 | 0x01777711 | A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 A2: 1-3 A1: 1-3 A0: 0-1 |
| RTCNT | 0xFF800020 | 0xA500 | RTCNT Write Code A5h Data 00h |
| RTCOR | 0xFF800024 | 0xA50D | Write code A5, data 0D (~15us)? |
| RTCSR | 0xFF80001C | 0xA518 | RTCSR Write Code A5h Data 18h |
| SDMR2 | 0xFF940088 | any | SDMR2 address on 32-bit bus Area3 CAS2 |
| MCR | 0xFF800014 | 0x101101B4 | RASD:'0' MRSET:'0' TRC=6 TCAS=1 TPC=3 RCD=2 TRWL=0 TRAS=4+TRC SZ=32 AMXEXT:'0' AMX=6 RFSH:'0' RMODE:'0' |
| 0x501101B4 | RASD:'0' MRSET:'1' TRC=6 TCAS=1 TPC=3 RCD=2 TRWL=0 TRAS=4+TRC SZ=32 AMXEXT:'0' AMX=6 RFSH:'0' RMODE:'0' |
| RFCR | 0xFF800028 | 0xA400 | RFCR Write Code A4h Data 00h |
- SDRAM(IC42S16800-7T ICSI製)
| Symbol | Parameter | CL | Min. | Max. | Units |
|---|
| t_CK3 | CLK Cycle time | CL=3 | 7.5 | | ns |
| t_CK2 | CL=2 | 10 | | ns |
| t_AC3 | CLK to valid output delay | CL=3 | | 5.4 | ns |
| t_AC2 | CL=2 | | 6 | ns |
| t_CH | CLK high pulse time | | 2.5 | | ns |
| t_CL | CLK low pulse time | | 2.5 | | ns |
| t_CKE | CKE setup time | | 1.5 | | ns |
| t_CKH | CKE hold time | | 0.8 | | ns |
| t_AS | Address setup time | | 1.5 | | ns |
| t_AH | Address hold time | | 0.8 | | ns |
| t_CMS | Comamnd setup time | | 1.5 | | ns |
| t_CMH | Command hold time | | 0.8 | | ns |
| t_DS | Data input setup time | | 1.5 | | ns |
| t_DH | Data input hold time | | 0.8 | | ns |
| t_OH3 | Output data hold time | CL=3 | 2.7 | | ns |
| t_OH2 | CL=2 | 3 | | ns |
| t_LZ | CLK to output in low-Z | | 0 | | ns |
| t_HZ | CLK to output in H-Z | | 2.7 | 5.4 | ns |
| t_RC | ROW cycle time | | 67.5 | | ns |
| t_RAS | ROW active time | | 45 | 100K | ns |
| t_RCD | RAS to CAS deley | | 20 | | ns |
| t_RP | Row precharge time | | 20 | | ns |
| t_RRD | Row active to active deley | | 15 | | ns |
| t_T | Transition time | | 1 | 10 | ns |
| t_RSC | Mode reg. set cycle | | 15 | | ns |
| t_PDE | Power down exit setup time | | 7.5 | | ns |
| t_SRX | Self refresh exit time | | 7.5 | | ns |
| t_DPL | Data in to Precharge | | 15 | | ns |
| t_DAL | Data in to Active/Refresh Deley time | | 35 | | ns |
| t_REF | Refresh Time | | | 64 | ms |
- SH7751Rバスタイミング(HD6417751RF240) 表23.26より抜粋
| 項目 | Symbol | Min. | Max. | Unit |
|---|
| アドレス遅延時間 | t_AD | 1.5 | 6 | ns |
| BS遅延時間 | t_BSD | 1.5 | 6 | ns |
| CS遅延時間 | t_CSD | 1.5 | 6 | ns |
| RW遅延時間 | t_RWD | 1.5 | 6 | ns |
| RD遅延時間 | t_RSS | 1.5 | 6 | ns |
| 読み出しデータ・セットアップ時間 | t_RDS | 3.5 | | ns |
| 読み出しデータ・ホールド時間 | t_RDH | 1.5 | | ns |
| WE遅延時間(立ち上がりエッジ時) | t_WEDF | | 6 | ns |
| WE遅延時間 | t_WEDI | 1.5 | 6 | ns |
| 書込みデータ遅延時間 | t_WDD | 1.5 | 6 | ns |
| RDYセットアップ時間 | t_RDYS | 3.5 | | ns |
| RDYホールド時間 | t_RDYH | 1.5 | | ns |
| RAS遅延時間 | t_RASD | 1.5 | 6 | ns |
| CAS遅延時間 | t_CASD | 1.5 | 6 | ns |
| CKE遅延時間 | t_CKED | 1.5 | 6 | ns |
| DQM遅延時間 | t_DQMD | 1.5 | 6 | ns |
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