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SM501

WPAのUSBポート

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SM501のUSBCanon PTP extensionsポートを動かす

Documentation

SM501デバイスドライバ

SM501のレジスタへのアクセスはioctlシステムコールを, VRAMへのアクセスはLinuxのフレームバッファアーキテクチャの一部を用います。

Linuxフレームバッファアーキテクチャは, Geert Uytterhoeven <geert@linux-m68k.org> によって維持されているアーキテクチャで,最新バージョンは2001年5月10日です。 詳細については,「Appendix-A: Frame Buffer Devices」を参照願います。 (正確を期すため,原文のまま掲示しています。)

レジスタへのアクセス

SM501レジスタへのアクセスにはioctlを用います。 ioctlの使用にはターゲットアーキテクチャのヘッダファイルが必要です。

# cp -R linux/include/asm-sh /usr/local/sh4-linux/include/asm

レジスタ値を読み込み,変更し,書き込むサンプルコードを以下に示します。

int reg32;
int value = 0xab;
int mask = 0x0000ff00;

// open device node
int fd  = open("/dev/fb0", O_RDWR);

// set MMIO address
ioctl(fd, 0, address);

// read register value
ioctl(fd, 1, &reg32);

// change register value
reg32 &= ~mask;
reg32 |= value << 8;

// write register value
ioctl(fd, 2, reg32);

レジスタ値変更の際,予約されているビットを変更しないように注意してください。

画面解像度設定

画面解像度,ビデオタイミング信号,ドットクロック等は SM501レジスタによって完全に制御されます。 レジスタ値を変更することによって画面解像度を動的に変更することが可能です。 画面解像度設定の際には以下の点に留意願います。

VRAMへのアクセス

SM501は7つのビデオプレーンを持っています。 本製品で使用するのは,以下の4つのプレーンです。

  1. アルファプレーン
  2. ビデオアルファプレーン
  3. ビデオプレーン
  4. グラフィックプレーン

詳細は添付のデータシートの1-12,1-23章を参照して下さい。

各プレーンにはフレームバッファのデバイスノードを通じてアクセスします。 フレームバッファの詳細はAppendix-Aを参照して下さい。 RGB565モードのグラフィックプレーン(fb0)にカラー画像data[3][w][h]を 描画するサンプルコードを以下に示します。

int xres, yres, size, i, j, idx, r, g, b;
unsigned char *ptr;

int fd  = open("/dev/fb0", O_RDWR);
size = xres * yres * 2;
ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);

for (j = 0; j < yres; ++j)
  for (i = 0; i < xres; ++i) {
      idx = (x + i) * 2 + (y + j) * xres * 2;
      r = data[0][j][i] >> 3;
      g = data[1][j][i] >> 2;
      b = data[2][j][i] >> 3;
      *((unsigned short int *)(ptr + idx)) = (r << 11) | (g << 5) | b;
    }
munmap(ptr, size);

SM501 is controled through MMIO registers,

that are handled as follows.

  1. Open dev/fb0:
    fd = open("/dev/fb0", O_RDWR);
  2. Set MMIO address as follows:
    ioctl(fd, 0, address)
  3. Read a register value as follows:
    int reg32;
    ioctl(fd, 1, &reg32)
  4. Write a value to the register as follows:
    ioctl(fd, 2, reg32)

SM501 is accessed through seven frame buffers.

They contain one video plane, two graphics planes, two alpha planes, and two hardware cursor planes. See SM501_MMCC_Databook pp.(1-12)-(1-13) for details of the video layers. Primary devices with display resolutions of VGA, SVGA, XGA, and SXGA (experimental) are considered in this document.

Each node is treated as a character device. See Documentation/fb/framebuffer.txt for details of the frame buffer. Just like MEM(4) device, a frame buffer is opened by OPEN(2):

fd = open("/dev/fb0", O_RDWR);

and mapped into memory by MMAP(2) to access:

p = (char *) mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);

See SM501_MMCC_Databook pp.(1-26)-(1-28) for details of the memory map and register space.

SXGA Modemodeline

Horizontal Total1850
Horizontal Sync Width130
Horizontal Sync start1280
Vertical Total1330
Vertical Sync Height2
Vertical Sync start1320

SM501 frame buffers and their memory address

are shown in the following table. The MMIO base address of the WPA is 0xa7e00000.

PriorityNameAddressNodeDescriptions
0Panel Plane0xa40c0000/dev/fb0Primary Graphics, image display
2Video Plane 00xa4340000/dev/fb1Video, videos from a ZV port
2Video Plane 10xa45c0000
3Video Alpha Plane0xa4840000/dev/fb2Video Alpha, image display
4Alpha Plane0xa4ac0000/dev/fb3Alpha, image display
1Panel Cursor Plane0xa4d40000/dev/fb4Primary Cursor, not used
0CRT Plane0xa4d50000/dev/fb5Secondary Graphics, not used
1CRT Cursor Plane0xa4fd0000/dev/fb6Secondary Cursor, not used

The Panel/CRT resolution is changed through register settings. It should be noted that Linux frame buffer-related information such as vinfo and finfo is no longer reliable except for the default resolution. A Panel/CRT timing signal should be turned off during the resolution change to avoid inappropriate timing signals.

The video alpha plane is disabled when a video plane is disabled. On the other hand, the alpha plane is independent of the video plane. Each buffer has a display priority. Priority 0 means the bottom layer, while priority 4 means the top layer.

Sample register settings

are shown in the following table.

OffsetValueDescription
0x000100x2ed547c0
0x000140x05126734
0x000080x00ff0000GPIO 31:0 Control
0x0000c0x00000000GPIO 63:32 Control
0x000380x00021877Current Gate
0x000400x00021877Power Mode 0 Gate
0x000480x00021877Power Mode 1 Gate
0x8001c0x00000000Panel Plane TL Location
0x800500x00000000Video Plane TL Location
0x800900x00000000Video Alpha TL Location
0x8010c0x00000000Alpha Plane TL Location
0x800400x00016203Video Display Control
0x800800x00010001Video Alpha Display Control
0x801000x00010001Alpha Display Control
0x802000x00010000CRT Display Control
0x900000x000022d1Capture Control
0x900040x001000b4Capture Clipping
0x900080x01e00280Chapture Size
0x900180x00000004Capture FIFO Control
XGA Kernel
0x9000c0x046c0000Capture Buffer 0 Address
0x900100x04840000Capture Buffer 1 Address
SXGA Kernel (experimental)
0x9000c0x00340000Capture Buffer 0 Address
0x900100x005c0000Capture Buffer 1 Address
VGA
0x000440x10090101Power Mode 0 Clock
0x0004C0x10090101Power Mode 1 Clock
0x800000x07013101Panel Display Control
0x800140x02800000Panel FB Width
0x800180x01e00000Panel FB Height
0x800240x033f027fPanel Horizontal Total
0x800280x004a028bPanel Horizontal Sync
0x8002c0x020c01dfPanel Vertical Total
0x800300x000201e9Panel Vertical Sync
0x800580x00000000Video Scale
0x800480x05000500Video FB Width
0x800100x05000500Panel FB Offset/Window Width
0x800880x05000500Video Alpha FB Offset/Window Width
0x801080x05000500Alpha FB Offset/Window Width
0x900140x00000500Capture Buffer Offset
0x800200x01df027fPanel Plane BR Location
0x800540x01df027fVideo Plane BR Locatoin
0x800940x01df027fVideo Alpha BR Location
0x801100x01df027fAlpha Plane BR Location
Bob
0x800580x08000000Video Scale
0x900000x000022b1Capture Control
SVGA
0x000440x08090101Power Mode 0 Clock
0x0004C0x08090101Power Mode 1 Clock
0x800000x07010101Panel Display Control
0x800140x03200000Panel FB Width
0x800180x02580000Panel FB Height
0x800240x040f031fPanel Horizontal Total
0x800280x00770357Panel Horizontal Sync
0x8002c0x02990257Panel Vertical Total
0x800300x0005027cPanel Vertical Sync
0x800580x0ccc0cccVideo Scale
0x800480x06400640Video FB Width
0x800100x06400640Panel FB Offset/Window Width
0x800880x06400640Video Alpha FB Offset/Window Width
0x801080x06400640Alpha FB Offset/Window Width
0x900140x00000640Capture Buffer Offset
0x800200x0257031fPanel Plane BR Location
0x800540x0257031fVideo Plane BR Locatoin
0x800940x0257031fVideo Alpha BR Location
0x801100x0257031fAlpha Plane BR Locatoin
Bob
0x800580x06670cccVideo Scale
0x900000x000022b1Capture Control
XGA
0x000440x01090101Power Mode 0 Clock
0x0004C0x01090101Power Mode 1 Clock
0x800000x07013101Panel Display Control
0x800140x04000000Panel FB Width
0x800180x03000000Panel FB Height
0x800240x052f03ffPanel Horizontal Total
0x800280x00870417Panel Horizontal Sync
0x8002c0x032502ffPanel Vertical Total
0x800300x00050302Panel Vertical Sync
0x800580x0a000a00Video Scale
0x800480x08000800Video FB Width
0x800100x08000800Panel FB Offset/Window Width
0x800880x08000800Video Alpha FB Offset/Window Width
0x801080x08000800Alpha FB Offset/Window Width
0x900140x00000800Capture Buffer Offset
0x800200x02ff03ffPanel Plane BR Location
0x800540x02ff03ffVideo Plane BR Locatoin
0x800940x02ff03ffVideo Alpha BR Location
0x801100x02ff03ffAlpha Plane BR Location
Bob
0x800580x05000a00Video Scale
0x900000x000022b1Capture Control
SXGA (experimental)
0x000440x00090101Power Mode 0 Clock
0x0004C0x00090101Power Mode 1 Clock
0x800000x07013101Panel Display Control
0x800140x05000000Panel FB Width
0x800180x04000000Panel FB Height
0x800240x06a704ffPanel Horizontal Total
0x800280x01600514Panel Horizontal Sync
0x8002c0x043403ffPanel Vertical Total
0x800300x001a0400Panel Vertical Sync
0x800580x07800780Video Scale
0x800480x0a000a00Video FB Width
0x800100x0a000a00Panel FB Offset/Window Width
0x800880x0a000a00Video Alpha FB Offset/Window Width
0x801080x0a000a00Alpha FB Offset/Window Width
0x900140x00000800Capture Buffer Offset
0x800200x03ff04ffPanel Plane BR Location
0x800540x03ff04ffVideo Plane BR Locatoin
0x800940x03ff04ffVideo Alpha BR Location
0x801100x03ff04ffAlpha Plane BR Location
Bob
0x800580x03c00800Video Scale
0x900000x000022b1Capture Control

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