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Feb. 2, 2004
Wireless & Visual Communication Co., Ltd.

Overview

wpa_s.jpg

WPAR is a reference board of wireless multimedia receiver, aiming to be an application development platform for wireless transmission of audio, image, and video contents.

It is equipped with Renesas SH7751R that works at 240MHz, which allows developers to take full advantage of fast and stable SH-Linux technologies.

A wireless network interface conformed with IEEE 802.11b is connected to WPAR via PC card slot, allowing for keeping up with the latest wireless LAN standards such as IEEE 802.11a and IEEE 802.11g by upgrading the network card.

WPAR's outstanding graphics capability is realized with two controller chips: Silicon Motion's SM501 for 2D image rendering, and VWeb's VW2010 for audio and video decoding. SM501 has several video layers including two graphics layers, two alpha layers, and a video layer, which are utilized for smooth display of image sequences with double buffering, and for building window GUIs. VW2010 supports a number of audio and video formats such as MPEG-1/2/4, their audio layers, AC3, and so forth. The decoded video is simultaneously outputted as VGA and NTSC formats. In addition, VW2010 also has multiple video layers, which enables overlaying of captions and images on moving pictures. This powerful combination of graphics chips releases the CPU from video processing loads and allow it to run interactive tasks during video playing.

Finally, all these features are implemented with selected components in terms of power consumption and thermal emission. As a result, WPAR does not require cooling fans, thus, is the best solution for embedded applications.

Features

This device is formed by 4 functional blocks below:

  1. MPU block: controls whole device
  2. WLAN block: supports 802.11b external CardBus card
  3. Video block: MPEG-1/2/4 data is converted to the output signal to the video terminal and VGA terminal
  4. Image block: JPEG(software based design above the MMI and application software) data is Converted to the output signal to the RGB terminal These functional blocks should possess as follows. Functional constitution of the device is shown in Fig.2
  1. MPU block (Based on Renesus SH7751R/240MHz with open Linux OS)
    • Operating condition's setup of WLAN block
    • Operating condition's setup of Video block
    • UDP TCP/IP protocol
    • Buffer control of Video data process
    • Application function is synchronized with transmission.
    • Driver function for the WLAN control
    • Driver function for the Video block control
    • Driver function for Image block control
    • JPEG Decompression function provide XGA image resolution
  2. WLAN block
    • Compliant with 802.11b protocol
    • Specialized protocol for Audio and Video transmission procedure
  3. Video/image block
    • MPEG-1/2/4 data's extension
    • Decoding process for a projector's output signal by going through video and RGB(BGA) terminal
    • JPEG Decompression function provide XGA image resolution for RGB(VGA) terminal
  4. LED
    • Indication LED`s content is below (minimum)
      • Power source LED: shows the fact that power source is applied.
      • Status indication LED: shows a condition of the device
      • Link establishing
      • Data receiving
  5. The operation button or SW
    • Consists of the below buttons (minimum)
      • Button: displays related information such as SSID, IP address, channel number, resolution. Being used as reset button as well (long 5 sec. or more pushing)
      • Button: power source
      • SW: auto scan
      • Button: resolution

System

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Fig.1: Block Diagram
 
Table 1
CPUSH7751R 240MHzRenesas Technology
Main MemorySDRAM 64MB
Video RAM16MB (SM501), 8M(VW2010)
Flash ROM16MB
Graphic controlerSM501Silicon Motion, Inc.
Video codecVW2010VWEB
Wirelss LAN802.11a/b/gKey Stream
USBx1USB 1.1
Video outComposite, SNTSC
Audio outRCAx2Stereo
VGA outStandard VGAVGA upto SXGA
LEDx3
Button Switchx4
JTAG14 pin JTAG(H-UID) connector

Figure 1 shows the block diagram of the reference board. The SH7751R (Renesas) is a 32 bit RISC microprocessor. It consists of the SH-4 CPU working at 240MHz, MMU, PCI bus controller, and BSC. Those built-in functions lead to lower system costs. A flash ROM for file system, SDRAM for main memory, graphic controller, and GPIO are connected to the local bus, while a video codec LSI and card bus bridge are connected to the PCI bus. Finally, it is equipped with a USB-UART bridge for a serial console. Specifications of the reference board are given in Table 1.

The SM501 (Silicon Motion Inc.) is a graphic controller chip with direct CPU bus interfaces. 16MB video RAM enables high resolutions up to 1280 x 1024, including a 1280 x 768 wide screen. It supports hardware video overlay, video scaling, and color space conversion from YUV to RGB. Table 2 gives the details of SM501's multiple video layers.

The VW2010 (Vweb Corp.) is an audio and video codec chip that supports real time decoding of MPEG-1/2/4 and H.263 video stream as well as MPEG-1/2 audio layers AAC, and AC-3 audio stream. With 8MB external SDRAM, it supports adaptive field/frame motion compensation and DCT types for high quality video decoding. It outputs ITU-R BT656 video signals through video DAC leading to S and composite video connecter as well as audio signals through audio DAC to RCA plug. The video signal is also transmitted to the graphic controller, through ZV port, and it is displayed on the SM501 video layer. The VW2010 has multiple video planes: two graphic planes that support alpha blending a hardware cursor plane. Table 3 shows the supported video formats in detail.


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